Capacitance Extraction

Since the early 1950s, microwave circuits have evolved from discrete circuits to planar integrated circuits, then to multilayered and three-dimensional integrated circuits. With the increased circuit density, the multiconductor line in multilayered dielectric media has become the major form of the transmission line or interconnect. Multilayered routing reduces the area as well as the volume of the circuit. However, as a result, electromagnetic coupling among conductors greatly influences circuit performance. In some microwave integrated circuits, this coupling effect is utilized to construct compact circuit components, under most circumstances it is regarded as a parasitic effect that must be modeled accurately for verification of the circuit’s validity and performance. In the related field of very-large-scale integration (VLSI) circuits, electromagnetic coupling among interconnects is also becoming increasingly important. With the introduction of deep-sub-micrometer (DSM) semiconductor technologies, the on-chip interconnect wire can no longer be considered as an equipotential form of coupling AU:1 . The parasitic effects introduced by the wires display a scaling behavior that differs from that of active devices such as transistors, and these effects tend to gain importance as device dimensions are reduced and circuit speed is increased. In fact, they begin to dominate some of the relevant metrics of digital integrated circuits such as speed, energy consumption, and reliability. A typical recursive design flowchart of a state-of-the-art integrated circuit (IC) is shown in Fig. 1, where a postlayout step termed parasitic extraction precedes gate-level simulation. The task of parasitic extraction is to model the electromagnetic effects of the wire with parasitic components of capacitance, resistance, and inductance, so that a more accurate circuit simulation can be performed. With the increase in working frequency and development of silicon technologies, the discrepancy between the microwave IC and the common VLSI circuit becomes marginal. Therefore, the electromagnetic modeling and accurate extraction of the interconnect parasitics have become a subject of advanced research in both fields to date. Among the three parasitic parameters, capacitance has attracted the most attention because it greatly influences time delay, power consumption, and the signal integrity and its calculation becomes complicated under DSM technologies. In the following sections, the fundamental theory and contemporary methodology and algorithms of capacitance extraction will be discussed.